Turning to FIGS. 1 and 2, an example of a conventional pipelined ADC 100 can be seen. ADC 100 generally comprises a pipeline (which receives an analog input signal AIN) that provides digital signals to a digital output circuit 108 so that a digital output signal DOUT can be generated. The pipeline is generally comprised of a sample-and-hold (S/H) circuit 102, ADC stages 104-1 to 104-N (which are generally arranged in a sequence), and sub-ADC 106. Each of the ADC stages 102-1 to 102-N generally comprises a sub-ADC 202, digital-to-analog converter (DAC) 204, an adder 206, and a residue amplifier 208. In operation, as shown in this example, S/H circuit 102 receives an analog input signal AIN and samples the signal based on sample signal SAMPLE. Each stage 104-1 to 104-N resolves a predetermined number of bits and passes its residue onto the next stage. To do this, sub-ADC 202 generates a digital representation of its input signal (either from the S/H circuit 102 or the previous stage); this digital representation is then provided to output circuit 108 and DAC 204. Residue amplifier 122 then amplifies the difference between the input signal (either from the S/H circuit 102 or the previous stage) and the output from DAC 204 from adder 206, which is the residue signal or residue of the stage. The final stage 104-N of the sequence then provides its residue to sub-ADC 106, which provides its digital representation of the residue from stage 104-N to digital output circuit 106.
One issue that arises with ADC 100 is interstage gain. This gain should be very accurate to maintain good linearity performance, and in order to generate this high accuracy gain a large open loop gain for the residue amplifier is employed. As technology scales to shorter channel lengths, supply voltages drop, and it becomes difficult to design the residue amplifier 208 for each of stages 104-1 to 104-N so as to have sufficiently high gain. Thus, there is a need for an improved pipelined ADC.
Some other conventional circuits are: S. H. Lewis, “Optimizing the stage resolution in pipelined, multistage, analog-to-digital converter for video-rate applications,” IEEE Trans. Circuits Syst II, Analog Digit. Signal Process., vol. 39, no. 8, pp. 516-523, August 1992; Panigada et al., “Digital background correction of harmonic distortion in pipelined ADCs,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 9, pp. 1885-1895, September 2006; Keane et al., “Background interstage gain calibration technique for pipelined ADCs,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 1, pp. 32-43, January 2005; Van de Vel et al., “A 1.2V 250 mW 14 b 100 MS/s digitally calibrated pipeline ADC in 90 nm CMOS,” VLSI Circuits, 2008 IEEE Symposium on, pp. 74-75, 18-20 Jun. 2008; Lee et al., “A 65 nm CMOS1.2V 12 b 30 MS/s ADC with capacitive reference scaling,” Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, pp. 165-168, 21-24 Sep. 2008; Das et al., “A 10 mW 9.7ENOB 80 MSPS pipeline ADC in 65 nm CMOS process without any special mask requirement and with single 1.3V supply,” Custom Integrated Circuits Conference, 2009. CICC '09. IEEE, pp. 165-168, 13-16 Sep. 2009; Lee et al., “A 12 b 50 MS/s 3.5 mW SAR assisted 2-stage pipeline ADC,” VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 239-240, 16-18 Jun. 2010; Chen et al., “A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references,” ASIC, 2007. ASICON '07. 7th International Conference on, pp. 249-252, 22-25 Oct. 2007; Shih et al., “Reference refreshing cyclic analog-to digital and digital-to-analog converters,” IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 544-554, August 1986; Naraghi et al., “A 9 b 14 μW 0.06 mm2 PPM ADC in 90 nm digital CMOS,” Solid-State Circuits Conference—Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 168-169,169a, 8-12 Feb. 2009; Li et al., “Delay-Line-Based Analog-to-Digital Converters,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 56, no. 6, pp. 464-468, June 2009; Watanabe et al., “A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS,” Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on, pp. 271-274, 13-16 Dec. 2009; Kim et al., “Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter,”Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57, no. 1, pp. 18-30, January 2010; Straayer et al., “A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 4, pp. 805-814, April 2008; Park et al., “A 0.13 μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer,” Solid-State Circuits Conference—Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 170-171,171a, 8-12 Feb. 2009; Taylor et al., “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” Solid-State Circuits, IEEE Journal of, vol. 45, no. 12, pp. 2634-2646, December 2010; Maghari et al., “Noise-shaped integrating quantisers in ΔΣ modulators,” Electronics Letters, vol. 45, no. 12, pp. 612-613, Jun. 4, 2009; Su et al., “A highly linear CMOS current-controlled oscillator using a novel frequency detector,” Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pp. 2841-2844, 18-21 May 2008; and U.S. Pat. No. 7,528,760.